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Intel Core 2 Extreme QX9650 - Penryn Architecture 2
Advanced Smart Cache
While the two cores of Wolfdale will share a 6MB cache, the Yorkfield shares a phenomenal 12MB cache. The increased performance of the larger caches comes from 24-way associativity, up from the 16-way of Conroe. Associativity essentially means there are more ways in an out of the cache, so data can be exchanged quicker. Think more entrances and exits into a large car park, only with data instead of cars. And fewer ticket machines.
Smart Memory Access
There's still an inefficient memory controller hub looking after things on Yorkfield - Intel isn't moving to an integrated controller a la AMD until Nehalem. To help hide the effects of this Intel uses a Memory Order Buffer, that employs smart prefetching algorithms that enable the chip to intelligently re-order instructions to reduce execution time in respect to load - Intel calls this Memory Disambiguation. The algorithm makes an educated guess about whether or not the chip can move on to the next set of instructions.
Advanced Digital Media Boost - SSE4.1
This is the big one for Penryn - the introduction of SSE 4.1 (Streaming SIMD Extensions), which adds 49 new instructions, the most added to SSE since 144 were added to the Pentium 4. These are focused on improving video encoding and decoding, and gaming. The best thing is that applications such as DivX 6.7 are already geared up to take advantage of these as well as the Japanese version of TPMPEG and we can expect other codecs to follow.
Deep Power Down
Deep Power Down technology will only be applicable to the mobile CPUs, which will simply be called Penryn, and is designed to really increase battery life through smart power saving techniques. This is especially important as quad-core comes to the mobile space.
Inevitably, all four cores are unlikely to be used at the same time. Therefore it's necessary to be able to put the parts of the CPU that aren't being used into a deep low power state, so that they are not a burden on the battery, while also being able to wake up quickly when they are needed. Intel claims that Deep Power Down enables the unused core to idle at with nearly zero power draw, which is quite an achievement.
There are five different power states ranging from full tilt to boring PowerPoint presentation mode, where the core is virtually asleep. We covered these here so I won't recap the whole thing again.
The deepest power stage is C6 and when this occurs the micro-architectural state is put into storage and the voltage is dropped. The only power goes to the SRAM where the state is stored and the IO ring that communicates with the chipset so it knows when to wake up.
The C6 state only occurs on a die basis - so in a dual-core mobile CPU it would only drop into C6 when there was no activity whatsoever. However, as Yorkfield is still two Wolfdale's stuck together, it would mean when only two cores were in use the other two could fall into C6 state - really saving power. You're quad core would only be more of a drain than a dual-core then, when it really needed to be.
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