Intel Talks Nehalem

Papers released at the VLSI symposia spill (some of) the beans.

Intel held a conference call yesterday evening, prior to the VLSI Symposia 2008, wherein Rajesh Kumar, Intel’s Director of Intel Circuit and Low Power Technologies, fed us some new information on Intel’s next architecture: Nehalem. As you’re all doubtless curious to know what we know about this next ‘tock’ in Intel’s process/architecture ‘tick/tock’ strategy we thought we’d share.

Kumar mentioned that Nehalem is the broad name covering the entire new architecture from server, through desktop to mobile CPUs, much in the same way as Penryn covered the entire 45nm process-shrink.

Nehalem’s architecture is radically different from Core 2 and has been designed from the ground up to be more modular and scalable. Internally the processing cores, memory controller and I/O centre are all decoupled as regards voltages and frequencies – each works in an environment that’s best for it. Unlike Intel’s rivals’ asynchronous solutions, though, as was pointed out, these modules are designed to be linked to synchronous interfaces – offering better performance and lower latencies.

Cores speak to each other on the same die via 6.4GT/s QPI links offering 25G/s of bandwidth. Kumar said that this is “three times better than our best competition today” – by which he means HyperTransport, as used by AMD. With three-channel DDR3 running at 1,333MHz Nehalem should get 32GB/s of memory bandwidth.

More fundamentally it was discussed that Nehalem, at least internally, isn’t really clock-rated any more. The cores are much more adaptive to external conditions, such as the voltage being fed to them, and the performance characteristics will change every cycle to best suit those conditions. So if, for example, the voltage drops off one cycle the clock speed will lower itself as well helping reduce errors, and thus reducing wasted clock cycles.

Apparently there was talk about not giving chips a specific speed rating at all, but Intel’s customers didn’t like that idea. Internal averaging, then, means that to the outside world the Nehalem CPU will still appear to run as a fixed clock speed part. Interestingly, Intel also mentions that the Duty Cycle is able to adapt to lifetime stress and transistor variations. In layman’s terms if part of the CPU isn’t working (for example a few hundred KB of cache) it can be disabled without having to kill the whole CPU – although obviously performance will be hampered more and more if and when further failures occur.

What this means is that after a year or so you’re top-of-the-line CPU that has been running overclocked for most of that time could actually be slower than an entry-level product as the extra stress slowly kills it. Admittedly CPUs rarely die anyway so that likelihood is slim, but it does throw up some questions we’ll be looking for answers to.

All in all, interesting stuff and we should definitely see some interesting stuff at IDF later this year.

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