IDF Spring 2006

As Spring IDF 2006 kicks off, Justin Rattner takes the stage for the opening keynote.

All Core Microarchitecture chips have some key features that will greatly improve processing efficiency. First up, the Smart Cache model first seen in the Core Duo will be rolled out across the range. This means that all the cores in a chip will share a single bank of Level 2 cache, so if one core is not being utilised, the second core will have access to all the Level 2 cache. The pre-cache system has also been improved with new algorithms ensuring that the chip is constantly fed with the data it needs, resulting in fewer wasted CPU cycles. Another piece in the puzzle is Intel Intelligent Power Capability, which will allow areas of the chip to basically power down when not in use, again lowering the power draw and increasing the performance per watt ratio.

The bar chart above shows that over-clocking a CPU will reward you with a modest increase in performance but with a significant increase in power draw. However, when under-clocking a chip, the drop in performance is modest, while the drop in power draw is significant. But when you couple the reduction in clock frequency with the addition of a second core, the performance increase is potentially massive, while the increase in power is modest – as shown in the diagram below.

What you’re seeing below is an indication of how Intel’s next generation of chips will not only outperform the current generation by a significant margin, but will also draw far less power. Ultimately Intel is pushing the performance per watt envelope like never before.

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