Power States

The performance figures Intel quoted us were impressive, but we will naturally reserve comment until we’ve tested the new hardware in the lab and compared it to existing technology. We were told to expect a 20 per cent increase in gaming performance and 40 per cent increase in media performance with the faster bus, clock speed, larger cache and SSE4.

In the mobile arena the 45nm Merom replacement will remain on the same socket initially; however news through the grape vine hints that this may be set to change in Q407 or Q108. The deeper power down technology includes five power states:

C0 is the active state in which everything is running at full capacity.

C1 has a slightly reduced core voltage while the core clock has been turned off, but the motherboard power lines are kept alive and the data cache is kept intact. This means that the performance isn’t compromised and the wakeup time is extremely fast, but only a little power is saved.

C3 has the same core voltage drop as the C1 state, but now turns off the PLL’s and flushes the L1 cache, switching it off and losing the data. L2 data cache remains intact as it takes longer to fill than L1 holding a larger variety of more general program data. The consequence of turning more off is a longer wakeup time, however Intel’s chart shows no appreciable drop in idle power, and therefore increment in battery life. However, we were only provided with a simple description rather than accurate working numbers, so we will have to reserve a true judgement until they arrive.

C4 drops the core voltage again, as well as partially flushing the L2 cache on top of everything previously applied in the C3 state.

C6 the final power down state, is an almost complete shutdown of the CPU. There is a significant drop in core voltage and everything is now switched off to maximise battery life. The obvious down side to this state is that the resume time will be greater.

Intel implies the sleep states are seamless, automatic transitions rather than something you select like the hibernate or sleep functions within the OS.

Enhanced dynamic acceleration technology is Intel’s new performance booster, without exceeding the total power output limit (TDP in Watts). In a multi core platform, if fewer than all cores are being used by a limited number of threads then the CPU will actually overclock individual cores in order to crunch through the process faster. It then co-ordinates other cores into a deeper, lower power sleep state in order to compensate for the thermal increase. While details are still scarce on the degree of auto overclocking employed and how much performance increase it offers, it’s certainly an interesting technique. This could provide for more overclockable processors - the only downside we can see is that a deeper sleep state means that other cores take longer to wake up, leaving the system unresponsive and dedicated to its single task.

While the Core architecture increased the SSE instruction handling to 128-bit from 64bit, to afford a single clock SSE function execution for a 2x performance increase, Penryn improves on this further by adding a Super Shuffle Engine with SSE4. Basically, by shuffling SSE operations it allows the processor to optimise the unpacking, packing, aligning, wide shifting, insertion, extraction and setup for horizontal arithmetic functions for better performance by reducing latencies.

Intel stipulated that current motherboards would need to attain certain requirements before being able to run 45nm CPUs, despite being socket compatible. The motherboard can be made to work with a simple BIOS update, however they would also need to support certain power requirements and the new elevated bus frequencies.

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