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About this time last year Intel launched the Sonoma platform for notebooks, which was the second generation of Centrino. Accompanying Yonah is another new platform, this time called Napa. Now, if you’re a wine buff you’ll know that Intel is continuing its vinyard based naming strategy – nothing wrong with that, the Napa valley is beautiful.

Of course both Yonah and Napa are Intel’s codenames for the new parts, the real names that the marketing bods have thought up are – Intel Core Duo Processor and Mobile Intel 945 Express Chipset. I don’t know about you but I definitely prefer Yonah and Napa! Now don’t think that you won’t be able to get a single core mobile chip anymore because you can, and this little baby will be called Intel Core Solo Processor – you get it right?

There’s also a differentiator between the single and dual core chips in the model numbers, with the single core 1.66GHz Solo chip numbered T1300, while the dual core 1.66GHz Duo chip is numbered T2300. The Duo range goes up from there to the T2400 at 1.83GHz, the T2500 at 2.0GHz and the T2600 at 2.16GHz. Looking at the pricing chart below, it’s clear that the T2400 is the sweet spot when it comes to price/performance.

Expect to see ultra-portable notebooks appearing with the low voltage Yonah chips. These are rather unimaginatively named Intel Core Duo Processor LV. The model numbers also reflect the low voltage angle with L2300 1.5GHz chip and the L2400 1.66GHz chip.

So, if you’ve got used to the very familiar “Intel Centrino Mobile Technology” moniker you’ll now have to get used to “Intel Centrino Duo Mobile Technology” for the next generation of dual core notebooks.

Intel has also implemented a new shared cache model with Yonah. Whereas the desktop dual core chips have separate Level 2 cache allocated to each core, with Yonah both cores share the single 2MB of L2 cache. This design can potentially provide a far more efficient execution environment. If you have separate Level 2 cache for each core and one core is heavily loaded while the other is twiddling its thumbs, that second block of cache is essentially useless. With the shared cache model, if one core if very busy it will take advantage of the majority of the Level 2 cache while the second core has no use for it. Of course if both cores are loaded they will have to share the cache, but that’s no different to if they had separate complements.

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