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Intel Core 2 Extreme QX9650 - Penyrn Architecture - Radix-16/Super Shuffle
Intel has created two new processors on the new 45nm process. Penryn, as I said earlier is an enhancement and refinement of the excellent Core architecture that powers current Core 2 Duos, while the other is Silverthorne, which is a low power CPU being aimed at the new Ultra Mobile PCs that should appear next year.
The desktop version of Penryn will be a native dual-core processor, known as Wolfdale. The quad-core variant, essentially two Wolfdales bolted together, is called Yorkfield. The Extreme model, a Yorkfield XE, with an unlocked multiplier, is being released on November 12th and is the processor we were sent for review. This is based on a 1,333MHz front-side bus, but we can expect faster clocked versions, based on a 1,600MHz front-side bus to appear later.
The 45nm die for the dual-core Wolfdale now sports 410 million transistors on a 107mm2 die, a 40 per cent increase over Conroe, which was 291 million transistors on a 143mm2 die. That's the benefit of die shrinks - more in less.
While it may not be a new architecture, there are several key areas where Penryn improves on Conroe and we'll now take a look at them in turn.
The first improvements we're getting to is the one that sounds like a washing powder. Radix-16 Divider. Simple Dynamic Execution refers to a dealing with instructions in as efficient a way as possible. There are a number of techniques to do this - data flow analysis, speculative execution, out of order execution, and super scalar architecture, all of which were first introduced with the great Pentium Pro, back in 1995. The Core architecture improved on this with Wide Dynamic Execution, which increased the number of instructions clocks per it could deal with.
One aspect of the Wide Dynamic Execution that's improved is how it deals with Radix computations - an algorithm that commonly used, especially in gaming. Previously this was a Radix-4 divider, working on two bits of data per iteration. Penryn though, has a Radix-16 divider enabling it to work on four bits of data per iteration, exactly doubling performance of this function. The best bit is that it requires no extra coding or new software - it just works.
Super Shuffle Engine
The SSE instructions that have been present in Intel processors since Pentium III, require a lot of operations on the data. This can now be done in a single clock cycle as the engine is now 128-bits wide, matching the length of SSE instructions - double that of Conroe.
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